module harness;
	logic clk_100;
	logic rst_n;
	logic test_mode = 0;
	logic scan_en;
	logic sram_clk;
	logic sram_cs_a_n;
	logic sram_cs_b_n;
	logic sram_we_a_n;
	logic sram_we_b_n;
	logic [9:0] sram_addr_a;
	logic [9:0] sram_addr_b;
	wire [23:0] sram_data_a;
	wire [23:0] sram_data_b;
	
	spt_interface u_spt_if(.clk(clk_100),
						   .rst_n(rst_n));
	mpi_interface u_mpi_if(.clk(clk_100),
						   .rst_n(rst_n));

	top U_top(
		.clk_100m (clk_100),
		.rst_n (rst_n),
		.test_mode (test_mode),
		.scan_en (scan_en),

		.CPU_CS_N (u_mpi_if.mpi_cs_n),
		.CPU_RD_N (u_mpi_if.mpi_rd_n),
		.CPU_WE_N (u_mpi_if.mpi_we_n),
		.CPU_ADDR (u_mpi_if.mpi_addr),
		.CPU_RDY_N (u_mpi_if.mpi_rdy_n),
		.CPU_DATA (u_mpi_if.mpi_data),

		.vid_in (u_spt_if.vld),
		.data_in (u_spt_if.data),
		.vid_out (u_spt_if.vld_out),
		.data_out (u_spt_if.data_out)
	);

	initial begin
		clk_100 = 1'b0;
		forever begin
			#5 clk_100 = ~clk_100;
		end
	end
	
	initial begin
		rst_n = 1'b1;
		#10  rst_n = 1'b0;
		#200 rst_n = 1'b1;
	end
	
	initial begin
		virtual spt_interface v_spt_if;
		virtual mpi_interface v_mpi_if;
		
		v_spt_if = u_spt_if;
		uvm_config_db #(virtual spt_interface)::set(null,"*spt_if_agent*","vif",v_spt_if);
		v_mpi_if = u_mpi_if;
		uvm_config_db #(virtual mpi_interface)::set(null,"*mpi_if_agent*","vif",v_mpi_if);
	
		run_test();
	end
	

	///gen fsdb wave
	initial begin
		$fsdbDumpfile("tc.fsdb");
		$fsdbDumpvars;
	end
endmodule
